A necessary component that enables compiler optimizations is a representation of control flow and data flow, typically contained in a Control Flow Graph and a Data Flow Graph (CDFG). For sequential programming languages, such as C or C++, the construction of a CDFG is well understood. For concurrent languages, such as a hardware description language (HDL), a traditional CDFG cannot adequately represent all the semantics of the language, such as the representation of statements executing concurrently, the notion of time, or hierarchical references. HDLs are frequently used to specify circuit designs for an integrated circuit (IC), such as a field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like. An electronic design automation (EDA) tool compiles HDL code specifying a circuit design for implementation in a target IC.
Example HDLs include Verilog, SystemVerilog, and VHDL. In such HDLs, control flow can be broken with delays or event triggers. Unlike sequential languages, a sequential block of instructions in HDL code may not actually execute consecutively. Some statements inside a sequential block cannot proceed without detecting an event, and the subsequent execution of the sequential block can be altered by other instructions executing simultaneously. In HDLs, the presence of hierarchical references breaks the locality of data flow. Therefore, controlling of dataflow are not efficiently modeled in HDL designs.